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| Standard ICs 8-bit compatible shift / store register BU4094BC / BU4094BCF / BU4094BCFV The BU4094BC, BU4094BCF, and BU4094BCFV are shift / store registers, each consisting of an 8-bit register and an 8-bit latch. As the data in the shift register can be latched by an asynchronous strobe input, it is possible to hold the output in the data transfer mode. The tri-state parallel output can be connected directly with an 8-bit bus line. These registers are suitable for in-line / parallel data conversion, data receivers and other similar applications. *Logic circuit diagram SERIAL IN CLOCK 8-STAGE SHIFT REGISTER QS Q'S SERIAL OUTPUT 8-BIT LATCHES *Block diagram STROBE SERIAL IN CLOCK Q1 Q2 Q3 Q4 1 2 3 4 5 6 7 8 16 VDD 15 OUTPUT ENABLE 14 Q5 13 Q6 12 Q7 11 Q8 10 Q'S 9 QS STROBE OUTPUT ENABLE Q1 3-STATE OUTPUTS Q8 PARALLEL OUTPUTS VSS *Truth table CLOCK OUTPUT STROBE SERIAL IN ENABLE H H H L H L NC: No Change Parallel output Q1 L H NC Z NC Z Qn Qn-1 Qn-1 NC Z NC Z Serial output QS Q7 Q7 Q7 Q7 NC NC Q'S NC NC NC NC QS QS H H L X X X L H X X X X X: Irrelevant Z: High Impedance 1 Standard ICs BU4094BC / BU4094BCF / BU4094BCFV *Absolute maximum ratings (Ta = 25C) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Input voltage Symbol VDD Pd Topr Tstg VIN Limits - 0.5 ~ + 20 1000 (DIP), 500 (SOP) 400 (SSOP) - 40 ~ + 85 - 55 ~ + 150 - 0.5 ~ VDD + 0.5 Unit V mW C C V *Electrical characteristics otherwise noted, VSS = 0V, Ta = 25C) DC characteristics (unless Parameter Symbol Min. 3.5 Input high level voltage VIH 7.0 11.0 -- Input low level voltage VIL -- -- Input high level current Input low level current IIH IIL -- -- 4.95 Output high level voltage VOH 9.95 14.95 -- Output low level voltage VOL -- -- - 0.44 Output high level current IOH - 1.1 - 3.0 0.44 Output low level current IOL 1.1 3.0 Output high level disable current Output low level disable current IDH IDL -- -- -- Static current dissipation IDD -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 1.5 3.0 4.0 0.3 - 0.3 -- -- -- 0.05 0.05 0.05 -- -- -- -- -- -- 1.0 - 1.0 20 40 80 A A A mA mA V V A A V V Unit VDD (V) 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 10 15 5 10 15 15 15 5 10 15 VI = VDD, or GND VOH = 4.6V VOH = 9.5V VOH = 13.5V VOL = 0.4V VOL = 0.5V VOL = 1.5V VOUT = 15V VOUT = 0V IO = 0mA IO = 0mA VIH = 15V VIL = 0V -- -- Conditions 2 Standard ICs BU4094BC / BU4094BCF / BU4094BCFV Switching characteristics (unless otherwise noted, VSS = 0V, Ta = 25C, CL = 50pF) Parameter Symbol Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 100 50 40 100 50 40 350 125 95 230 110 75 420 195 135 290 145 100 140 75 55 140 75 55 20 8 6 10 10 5 100 50 40 NO Limit 1.25 2.5 3.0 -- -- -- -- 5 10 12.5 100 40 35 5 -- -- -- 200 80 70 -- Max. -- -- -- -- -- -- 600 250 190 460 220 150 840 390 270 580 290 200 280 150 110 280 150 110 125 55 35 40 20 15 200 100 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s MHz MHz MHz ns ns ns pF Conditions Measurement circuit Fig.1 VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 -- Output rise time tTLH -- Output fall time Propagation delay time, CLOCK to Qs Propagation delay time, CLOCK to Qs Propagation delay time, CLOCK to Qn Propagation delay time, STROBE to Qn 3-state propagation delay time, Output Enable to Qn 3-state propagation delay time, Output Enable to Qn Minimum setup time, DATA to CLOCK Minimum hold time, CLOCK to DATA Minimum clock pulse width Maximum clock rise time and fall time Maximum clock frequency Minimum strobe pulse width Input capacitance tTHL -- Fig.1 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPZH tPLZ tPZL -- Fig.1 -- Fig.1 -- Fig.1 -- Fig.1 RL = 1k Fig.2 RL = 1k Fig.2 tSU -- Fig.1 tH -- Fig.1 tW -- Fig.1 tr (CL) tf (CL) -- Fig.1 fCL -- Fig.1 tWH CIN -- -- Fig.1 -- 3 Standard ICs BU4094BC / BU4094BCF / BU4094BCFV *Measurement circuits VDD OUTPUT ENABLE DATA STROBE P.G. CLOCK 50pF P.G. OUTPUT OUTPUT ENABLE DATA STROBE CLOCK OUTPUT 1k 50pF A: tPLZ, tPZL B: tPHZ, tPZH SW A B GND GND Fig. 1 Switching waveform Fig. 2 3-state delay time tW CLOCK 50% tSU DATA 50% tH 50% tWH STROBE 50% 50% 50% 50% 50% tr 90% 10% tf 90% OUTPUT ENABLE tPLH Q1 ~ Q8 tTLH Qs 90% 50% 10% tTHL tPHL 90% 50% 10% tPLH 50% tPLH Q's tPLH 50% tPHZ 90% 50% tPZH 50% 50% tPLZ 50% tPZL 90% 10% tPHL 50% tPHL 50% 50% 10% Fig. 3 Switching time test waveform *Electrical characteristic curve 1200 POWER DISSIPATION: Pd (mW) 1000 DIP16 800 600 SOP16 400 SSOP - B16 200 0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE: Ta (C) Fig. 4 Power dissipation vs. ambient temperature 4 Standard ICs BU4094BC / BU4094BCF / BU4094BCFV *External dimensions (Units: mm) BU4094BC 19.4 0.3 16 9 6.5 0.3 BU4094BCF 10.0 0.2 16 6.2 0.3 4.4 0.2 9 1 0.51Min. 3.2 0.2 4.25 0.3 8 7.62 1 0.3 0.1 8 1.5 0.1 0.11 2.54 0.5 0.1 0 ~ 15 1.27 0.4 0.1 0.3Min. 0.15 DIP16 BU4094BCFV 5.0 0.2 16 4.4 0.2 9 SOP16 6.4 0.3 1.15 0.1 1 8 0.1 0.65 0.22 0.1 0.3Min. 0.1 SSOP-B16 0.15 0.1 0.15 0.1 5 |
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